In a typical semiconductor device, metal gates may be formed in trenches in an interlayer dielectric (ILD) by depositing various layers such as a high-k dielectric layer, work function (WF) layers such as titanium nitride (TiN) and titanium aluminum carbide (TiAlC), a gate metal such as tungsten (W) or aluminum (Al), and a capping layer. However, as semiconductor devices are scaled down, it is difficult to deposit the various layers without narrowing or pinching off the gate, which in turn causes poor fill for an organic planarization layer (OPL) and reactive ion etch (RIE) damage to the WF layers in recess formation in subsequent processing. Also, OPL removal is done by ashing, which causes a threshold voltage (Vt) shift and leakage increase. FIG. 1 illustrates a gate 101 formed in a trench in an ILD (not shown for illustrative convenience), for a 7 nm device. The gate has a 125 nm height (this gate height can be changed) and a 15 nm width, which represents a potential 15 nm opening for depositing the various layers. As shown in this figure, a gate oxide layer 103 is formed on the bottom surface, and then a conformal layer of a high-k dielectric 105 and WF layers of TiN 107, TiAlC 109 and TiN 111 are sequentially deposited on side and bottom surfaces of the trench. However, due to narrowing of the opening during formation of the gate layers, the actual opening for the metal fill may be less than 5 nm. The decreased metal opening size can cause the etching and recessing processes to fail, and increase the likelihood of a gate electrode to contact short.
A need therefore exists for methodology enabling the fabrication of a metal gate without narrowing or pinching off the gate and the resulting device.